rtl8019.h

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00001 /*##############################################################################
00002 
00003 nIP - nano IP stack
00004 
00005 File        : rtl8019.h
00006 
00007 Description : Communication with the NIC (header).
00008 
00009 Copyright notice:
00010 
00011 Copyright (C) 2005 -
00012 Andreas Dittrich, dittrich@informatik.hu-berlin.de
00013 Jon Kowal, kowal@informatik.hu-berlin.de
00014 
00015 This program is free software; you can redistribute it and/or
00016 modify it under the terms of the GNU General Public License
00017 as published by the Free Software Foundation; either version 2
00018 of the License, or (at your option) any later version.
00019 
00020 This program is distributed in the hope that it will be useful,
00021 but WITHOUT ANY WARRANTY; without even the implied warranty of
00022 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
00023 GNU General Public License for more details.
00024 
00025 You should have received a copy of the GNU General Public License
00026 along with this program; if not, write to the Free Software
00027 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
00028 
00029 ##############################################################################*/
00030 
00031 
00032 #ifndef _RTL_8019_H
00033  #define _RTL_8019_H
00034 
00035 
00036 #include "net/net_if.h"
00037 #include "nip_error.h"
00038 
00039 
00040 
00041 #define nop()  __asm__ __volatile__ ("nop" ::)
00042 
00043 /** @name Other configuration */
00044 //@{
00045 #define RTL_ETHER_MIN_SIZE     (64-4)
00046 #define RTL_ETHER_TRAILER_SIZE 4
00047 //@}
00048 
00049 
00050 /** @name Ethernet Card I/O Macros */
00051 //@{
00052 #define RTL_WR_ON()     ADDR_PORT_RLT |= _BV(WRITE_PIN);
00053 #define RTL_WR_OFF()    ADDR_PORT_RLT &= ~_BV(WRITE_PIN);
00054 
00055 #define RTL_RD_ON()     ADDR_PORT_RLT |= _BV(READ_PIN);
00056 #define RTL_RD_OFF()    ADDR_PORT_RLT &= ~_BV(READ_PIN);
00057 
00058 #define RTL_RESET_OFF() ADDR_PORT_RLT &= ~_BV(RESET_PIN);
00059 
00060 /** @name Ethernet Card I/O Configuration*/
00061 //@{
00062 #define DATA_CTRL_RLT         DDRA
00063 // Fuer ATMega128/32 wird bei ATMega102 nicht benutzt
00064 #define DATA_ADDR_RLT         DDRB
00065 #define ADDR_PORT_RLT         PORTB
00066 #define DATA_PORT_RLT_WRITE   PORTA //!< Write Port
00067 #define DATA_PORT_RLT_READ    PINA  //!< Read  Port
00068 #define WRITE_PIN      5            //!< gibt den Pin an WriteIO Signal angeschlossen
00069 #define READ_PIN       6            //!< gibt den Pin an ReadIO Signal angeschlossen
00070 #define RESET_PIN      7            //!< gibt den Pin an Reset angeschlossen ist
00071 #define INPUT          0x00         //!< setzt einen Port auf Input
00072 #define OUTPUT         0xff         //!< setzt einen Port auf Output
00073 //@}
00074 
00075 /** @name Ethernet Card Interrupt */
00076 //@{
00077 #define RTL_INTERRUPT  INT0_vect  /**< AVR INT0 vector */
00078 #define RTL_GICR_FLAG  _BV(INT0) /*1<<INT0*/  /**< AVR INT0 Global Interrupt Control Register Bit */
00079 #define RTL_CLEAR_ISR() WriteRTL ( RTL_ISR, 0xFF ) /**< Clear Interrupt Service Register (1<<PRX|1<<PTX|1<<RXE|1<<TXE|1<<OVW|1<<CNT|1<<RDC|1<<RST) */
00080 #define RTL_DISABLE_INT() GICR &= ~RTL_GICR_FLAG
00081 #define RTL_ENABLE_INT()  GICR |=  RTL_GICR_FLAG
00082 
00083 #if defined (__AVR_ATmega32__)
00084 #       if ( RTL_INTERRUPT == INT0_vect )
00085 #               define RTL_CONFIGURE_INT() MCUCR |= 0x03
00086 #       elif
00087 #               define RTL_CONFIGURE_INT() MCUCR |= 0x0C
00088 #       endif
00089 #endif
00090 
00091 //@}
00092 
00093 /** @name NE2000 compatible Network Interface Registers */
00094 //@{
00095 
00096 #define RTL_REG_OFFSET 96
00097 
00098 #define RTL_CR         RTL_REG_OFFSET+0x00 /**< Command Register */
00099 
00100 #define RTL_8019ID0    RTL_REG_OFFSET+0x0A /**< 8019 ID Register 0, should be 0x50 after hard- and software reset*/
00101 #define RTL_8019ID1    RTL_REG_OFFSET+0x0B /**< 8019 ID Register 1, should be 0x70 after hard- and software reset*/
00102 #define RTL_RCR        RTL_REG_OFFSET+0x0C /**< Receive Configuration Register (W-Page0,R-Page2)*/
00103 #define RTL_TCR        RTL_REG_OFFSET+0x0D /**< Transmit Configuration Register(W-Page0,R-Page2)*/
00104 #define RTL_DCR        RTL_REG_OFFSET+0x0E /**< Data Configuration Register (W-Page0,R-Page2)*/
00105 #define RTL_IMR        RTL_REG_OFFSET+0x0F /**< Interrupt Mask Register (W-Page0,R-Page2)*/
00106 
00107 #define RTL_PSTART     RTL_REG_OFFSET+0x01 /**< Page Start register (W-Page0,R-Page2) */
00108 #define RTL_PSTOP      RTL_REG_OFFSET+0x02 /**< Page Stop register  (W-Page0,R-Page2) */
00109 #define RTL_BNRY       RTL_REG_OFFSET+0x03 /**< Boundary Register (R/W-Page0). Holds a pointer indicating the last receive buffer page the host has read. */
00110 #define RTL_TPSR       RTL_REG_OFFSET+0x04 /**< Transmit Page Start Register (W-Page0) */
00111 #define RTL_TBCR0      RTL_REG_OFFSET+0x05 /**< Transmit Bytes Count Register (LOW) (W-Page0) */
00112 #define RTL_TBCR1      RTL_REG_OFFSET+0x06 /**< Transmit Bytes Count Register (HIGH)(W-Page0) */
00113 #define RTL_ISR        RTL_REG_OFFSET+0x07 /**< Interrupt Status Register (R/W-Page0) */
00114 #define RTL_RSAR0      RTL_REG_OFFSET+0x08 /**< Remote Start Address Register (LOW) (W-Page0) */
00115 #define RTL_RSAR1      RTL_REG_OFFSET+0x09 /**< Remote Start Address Register (HIGH)(W-Page0) */
00116 #define RTL_CRDA0      RTL_REG_OFFSET+0x08 /**< Current Remote DMA Address (LOW) (R-Page0) */
00117 #define RTL_CRDA1      RTL_REG_OFFSET+0x09 /**< Current Remote DMA Address (HIGH)(R-Page0) */
00118 #define RTL_RBCR0      RTL_REG_OFFSET+0x0A /**< Remote Byte Count Register (LOW) (W-Page0)*/
00119 #define RTL_RBCR1      RTL_REG_OFFSET+0x0B /**< Remote Byte Count Register (HIGH)(W-Page0)*/
00120 #define RTL_RSR        RTL_REG_OFFSET+0x0C /**< Receive Status Register (R-Page0)*/
00121 #define RTL_CNTR0      RTL_REG_OFFSET+0x0D /**< Frame Alignment Error Tally Counter Register (R-Page0)*/
00122 #define RTL_CNTR1      RTL_REG_OFFSET+0x0E /**< CRC Error Tally Counter Register (R-Page0) */
00123 #define RTL_CNTR2      RTL_REG_OFFSET+0x0F /**< Missed Packet Tally Counter Register (R-Page0) */
00124 
00125 #define RTL_PAR0       RTL_REG_OFFSET+0x01 /**< Physical Address Register 0 (R/W-Page1)*/
00126 #define RTL_PAR1       RTL_REG_OFFSET+0x02 /**< Physical Address Register 1 (R/W-Page1)*/
00127 #define RTL_PAR2       RTL_REG_OFFSET+0x03 /**< Physical Address Register 2 (R/W-Page1)*/
00128 #define RTL_PAR3       RTL_REG_OFFSET+0x04 /**< Physical Address Register 3 (R/W-Page1)*/
00129 #define RTL_PAR4       RTL_REG_OFFSET+0x05 /**< Physical Address Register 4 (R/W-Page1)*/
00130 #define RTL_PAR5       RTL_REG_OFFSET+0x06 /**< Physical Address Register 5 (R/W-Page1)*/
00131 #define RTL_CURR       RTL_REG_OFFSET+0x07 /**< Current Page Register (R/W-Page1). Newly received packets will be added to the address in CURR. */
00132 #define RTL_MAR0       RTL_REG_OFFSET+0x08 /**< Physical Address Register 0 (R/W-Page1)*/
00133 #define RTL_MAR1       RTL_REG_OFFSET+0x09 /**< Physical Address Register 1 (R/W-Page1)*/
00134 #define RTL_MAR2       RTL_REG_OFFSET+0x0A /**< Physical Address Register 2 (R/W-Page1)*/
00135 #define RTL_MAR3       RTL_REG_OFFSET+0x0B /**< Physical Address Register 3 (R/W-Page1)*/
00136 #define RTL_MAR4       RTL_REG_OFFSET+0x0C /**< Physical Address Register 4 (R/W-Page1)*/
00137 #define RTL_MAR5       RTL_REG_OFFSET+0x0D /**< Physical Address Register 5 (R/W-Page1)*/
00138 
00139 #define RTL_RDMAPORT   RTL_REG_OFFSET+0x10 /**< Remote DMA Port (0x10-0x17)*/
00140 #define RTL_RSTPORT    RTL_REG_OFFSET+0x18 /**< Reset Port (0x18-0x1F)*/
00141 //@}
00142 
00143 
00144 /** @name RTL8019AS initial register values */
00145 //@{
00146 #define RCRVAL_CHECK_PHY     0x0C /* 0x04-Broadcast + 0x08-Multicast*/
00147 #define RCRVAL_IGN_PHY       0x1C /* 0x04-Broadcast + 0x08-Multicast + 0x10-No-Unicast-Check */
00148 #define TCRVAL     0x00
00149 #define DCRVAL     0x58
00150 //@}
00151 
00152 
00153 /** @name Initial Page Addresses */
00154 //@{
00155 #define RTL_TXSTART    0x40
00156 #define RTL_RXSTART    0x46
00157 #define RTL_RXSTOP     0x60
00158 //@}
00159 
00160 /** @name NE2000 ISR Register Bits */
00161 //@{
00162 #define RTL_ISR_PRX   0x01 /**< BIT 0 This bit indicates packet received with no error */
00163 #define RTL_ISR_PTX   0x02 /**< BIT 1 This bit indicates packet transmitted with no error */
00164 #define RTL_ISR_RXE   0x04 /**< BIT 2 This bit is set when a packet received contained an error */
00165 #define RTL_ISR_TXE   0x08 /**< BIT 3 Transmit Error Bit is set when packet transmission is aborted due to excessive collitions. */
00166 #define RTL_ISR_OVW   0x10 /**< BIT 4 This bit is set when the receive buffer is exhausted */
00167 #define RTL_ISR_CNT   0x20 /**< BIT 5 Set when the MSB of one or more of the tally counters has been set */
00168 #define RTL_ISR_RDC   0x40 /**< BIT 6 Set when remote DMA operation has been completed */
00169 #define RTL_ISR_RST   0x80 /**< BIT 7 This bit is set when NIC enteres reset state and is cleared, when a start command is issued to the CR */
00170 //@}
00171 
00172 /** @name NE2000 CR Register Bits */
00173 //@{
00174 #define RTL_CR_STP    0x01 /**< BIT 0 Stop Command */
00175 #define RTL_CR_STA    0x02 /**< BIT 1 Start Command (if STP==0) */
00176 #define RTL_CR_TXP    0x04 /**< BIT 2 Must be set to transmit a packet */
00177 #define RTL_CR_RD0    0x08 /**< BIT 3 Needed for Read/Send Commands */
00178 #define RTL_CR_RD1    0x10 /**< BIT 4 Needed for Write/Send Commands */
00179 #define RTL_CR_RD2    0x20 /**< BIT 5 Needed for Abort/Complete Command */
00180 #define RTL_CR_PS0    0x40 /**< BIT 6 Needed to select register page */
00181 #define RTL_CR_PS1    0x80 /**< BIT 7 Needed to select register page */
00182 //@}
00183 
00184 /** @name NE2000 CR Commands */
00185 //@{
00186 #define RTL_CR_STOP            RTL_CR_STP /**< (STA=0, STP=1) Stop command  */
00187 #define RTL_CR_START           RTL_CR_STA /**< (STA=1, STP=0) Start command */
00188 #define RTL_CR_TRANSMIT_PACKET RTL_CR_TXP /**< (TXP=1) Transmit Packet      */
00189 #define RTL_CR_RD_NOT_ALLOWED  0x00       /**< (RD0=0, RD1=0, RD2=0) not allowed  */
00190 #define RTL_CR_RD_REMOTE_READ  RTL_CR_RD0 /**< (RD0=1, RD1=0, RD2=0) remote read  */
00191 #define RTL_CR_RD_REMOTE_WRITE RTL_CR_RD1 /**< (RD0=0, RD1=1, RD2=0) remote write */
00192 #define RTL_CR_RD_SEND_PACKET  0x18       /**< (RD0=1, RD1=1, RD2=0) send packet  */
00193 #define RTL_CR_RD_ABORT_CMPLTE RTL_CR_RD2 /**< (RD0=0, RD1=0, RD2=1) abort/complete Remote DMA*/
00194 #define RTL_CR_SELECT_PAGE0    0x00       /**< (PS0=0, PS1=0) Select Register Page 0 */
00195 #define RTL_CR_SELECT_PAGE1    RTL_CR_PS0 /**< (PS0=1, PS1=0) Select Register Page 1 */
00196 #define RTL_CR_SELECT_PAGE2    RTL_CR_PS1 /**< (PS0=0, PS1=1) Select Register Page 2 */
00197 //@}
00198 
00199 /** @name NE2000 Control Macros */
00200 //@{
00201 #define RTL_START()     WriteRTL ( RTL_CR , (RTL_CR_START | RTL_CR_RD_ABORT_CMPLTE) )
00202 #define RTL_STOP()      WriteRTL ( RTL_CR , (RTL_CR_STOP  | RTL_CR_RD_ABORT_CMPLTE) )
00203 //@}
00204 
00205 typedef enum
00206 {
00207         RTL_RX_IDLE = 0, /**< receiving no packet */
00208         RTL_RX_NEW,      /**< new packet waiting */
00209         RTL_RX_READ_INIT,/**< read initialized (packet length read) */
00210         RTL_RX_READING   /**< reading packet data from chip */
00211 } rtl_rx_stat_t;
00212 
00213 typedef enum
00214 {
00215         RTL_TX_IDLE = 0 /**< sending no packet */
00216 } rtl_tx_stat_t;
00217 
00218 typedef struct
00219 {
00220         nip_net_if_id_t  id;      /**< network interface ID */
00221         nip_net_if_t    *conf;    /**< network interface configuration */
00222         rtl_rx_stat_t    rx_stat; /**< packet receive status */
00223         rtl_tx_stat_t    tx_stat; /**< packet transmission status */
00224 } rtl_if_stat_t;
00225 
00226 
00227 
00228 
00229 extern nip_net_if_id_t rtl_net_if_id;
00230 
00231 // Prototype
00232 
00233 nip_error_t   nip_rtl_send_init ( nip_net_if_id_t net_if_id, void *ll_target_addr, uint16_t type, void *daddr, void *saddr, uint16_t len);
00234 uint16_t      nip_rtl_send      ( nip_net_if_id_t net_if_id, uint8_t* buffer, uint16_t count);
00235 nip_success_t nip_rtl_read_init ( nip_net_if_id_t net_if_id );
00236 uint16_t      nip_rtl_read      ( nip_net_if_id_t net_if_id, uint8_t *buffer, uint16_t count);
00237 nip_success_t nip_rtl_open      ( nip_net_if_id_t net_if_id );
00238 nip_success_t nip_rtl_close     ( nip_net_if_id_t net_if_id );
00239 
00240 #endif // _RTL_8019_H
00241 
00242 

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