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00032 #ifndef _RTL_8019_H
00033 #define _RTL_8019_H
00034
00035
00036 #include "net/net_if.h"
00037 #include "nip_error.h"
00038
00039
00040
00041 #define nop() __asm__ __volatile__ ("nop" ::)
00042
00043
00044
00045 #define RTL_ETHER_MIN_SIZE (64-4)
00046 #define RTL_ETHER_TRAILER_SIZE 4
00047
00048
00049
00050
00051
00052 #define RTL_WR_ON() ADDR_PORT_RLT |= _BV(WRITE_PIN);
00053 #define RTL_WR_OFF() ADDR_PORT_RLT &= ~_BV(WRITE_PIN);
00054
00055 #define RTL_RD_ON() ADDR_PORT_RLT |= _BV(READ_PIN);
00056 #define RTL_RD_OFF() ADDR_PORT_RLT &= ~_BV(READ_PIN);
00057
00058 #define RTL_RESET_OFF() ADDR_PORT_RLT &= ~_BV(RESET_PIN);
00059
00060
00061
00062 #define DATA_CTRL_RLT DDRA
00063
00064 #define DATA_ADDR_RLT DDRB
00065 #define ADDR_PORT_RLT PORTB
00066 #define DATA_PORT_RLT_WRITE PORTA
00067 #define DATA_PORT_RLT_READ PINA
00068 #define WRITE_PIN 5
00069 #define READ_PIN 6
00070 #define RESET_PIN 7
00071 #define INPUT 0x00
00072 #define OUTPUT 0xff
00073
00074
00075
00076
00077 #define RTL_INTERRUPT INT0_vect
00078 #define RTL_GICR_FLAG _BV(INT0)
00079 #define RTL_CLEAR_ISR() WriteRTL ( RTL_ISR, 0xFF )
00080 #define RTL_DISABLE_INT() GICR &= ~RTL_GICR_FLAG
00081 #define RTL_ENABLE_INT() GICR |= RTL_GICR_FLAG
00082
00083 #if defined (__AVR_ATmega32__)
00084 # if ( RTL_INTERRUPT == INT0_vect )
00085 # define RTL_CONFIGURE_INT() MCUCR |= 0x03
00086 # elif
00087 # define RTL_CONFIGURE_INT() MCUCR |= 0x0C
00088 # endif
00089 #endif
00090
00091
00092
00093
00094
00095
00096 #define RTL_REG_OFFSET 96
00097
00098 #define RTL_CR RTL_REG_OFFSET+0x00
00099
00100 #define RTL_8019ID0 RTL_REG_OFFSET+0x0A
00101 #define RTL_8019ID1 RTL_REG_OFFSET+0x0B
00102 #define RTL_RCR RTL_REG_OFFSET+0x0C
00103 #define RTL_TCR RTL_REG_OFFSET+0x0D
00104 #define RTL_DCR RTL_REG_OFFSET+0x0E
00105 #define RTL_IMR RTL_REG_OFFSET+0x0F
00106
00107 #define RTL_PSTART RTL_REG_OFFSET+0x01
00108 #define RTL_PSTOP RTL_REG_OFFSET+0x02
00109 #define RTL_BNRY RTL_REG_OFFSET+0x03
00110 #define RTL_TPSR RTL_REG_OFFSET+0x04
00111 #define RTL_TBCR0 RTL_REG_OFFSET+0x05
00112 #define RTL_TBCR1 RTL_REG_OFFSET+0x06
00113 #define RTL_ISR RTL_REG_OFFSET+0x07
00114 #define RTL_RSAR0 RTL_REG_OFFSET+0x08
00115 #define RTL_RSAR1 RTL_REG_OFFSET+0x09
00116 #define RTL_CRDA0 RTL_REG_OFFSET+0x08
00117 #define RTL_CRDA1 RTL_REG_OFFSET+0x09
00118 #define RTL_RBCR0 RTL_REG_OFFSET+0x0A
00119 #define RTL_RBCR1 RTL_REG_OFFSET+0x0B
00120 #define RTL_RSR RTL_REG_OFFSET+0x0C
00121 #define RTL_CNTR0 RTL_REG_OFFSET+0x0D
00122 #define RTL_CNTR1 RTL_REG_OFFSET+0x0E
00123 #define RTL_CNTR2 RTL_REG_OFFSET+0x0F
00124
00125 #define RTL_PAR0 RTL_REG_OFFSET+0x01
00126 #define RTL_PAR1 RTL_REG_OFFSET+0x02
00127 #define RTL_PAR2 RTL_REG_OFFSET+0x03
00128 #define RTL_PAR3 RTL_REG_OFFSET+0x04
00129 #define RTL_PAR4 RTL_REG_OFFSET+0x05
00130 #define RTL_PAR5 RTL_REG_OFFSET+0x06
00131 #define RTL_CURR RTL_REG_OFFSET+0x07
00132 #define RTL_MAR0 RTL_REG_OFFSET+0x08
00133 #define RTL_MAR1 RTL_REG_OFFSET+0x09
00134 #define RTL_MAR2 RTL_REG_OFFSET+0x0A
00135 #define RTL_MAR3 RTL_REG_OFFSET+0x0B
00136 #define RTL_MAR4 RTL_REG_OFFSET+0x0C
00137 #define RTL_MAR5 RTL_REG_OFFSET+0x0D
00138
00139 #define RTL_RDMAPORT RTL_REG_OFFSET+0x10
00140 #define RTL_RSTPORT RTL_REG_OFFSET+0x18
00141
00142
00143
00144
00145
00146 #define RCRVAL_CHECK_PHY 0x0C
00147 #define RCRVAL_IGN_PHY 0x1C
00148 #define TCRVAL 0x00
00149 #define DCRVAL 0x58
00150
00151
00152
00153
00154
00155 #define RTL_TXSTART 0x40
00156 #define RTL_RXSTART 0x46
00157 #define RTL_RXSTOP 0x60
00158
00159
00160
00161
00162 #define RTL_ISR_PRX 0x01
00163 #define RTL_ISR_PTX 0x02
00164 #define RTL_ISR_RXE 0x04
00165 #define RTL_ISR_TXE 0x08
00166 #define RTL_ISR_OVW 0x10
00167 #define RTL_ISR_CNT 0x20
00168 #define RTL_ISR_RDC 0x40
00169 #define RTL_ISR_RST 0x80
00170
00171
00172
00173
00174 #define RTL_CR_STP 0x01
00175 #define RTL_CR_STA 0x02
00176 #define RTL_CR_TXP 0x04
00177 #define RTL_CR_RD0 0x08
00178 #define RTL_CR_RD1 0x10
00179 #define RTL_CR_RD2 0x20
00180 #define RTL_CR_PS0 0x40
00181 #define RTL_CR_PS1 0x80
00182
00183
00184
00185
00186 #define RTL_CR_STOP RTL_CR_STP
00187 #define RTL_CR_START RTL_CR_STA
00188 #define RTL_CR_TRANSMIT_PACKET RTL_CR_TXP
00189 #define RTL_CR_RD_NOT_ALLOWED 0x00
00190 #define RTL_CR_RD_REMOTE_READ RTL_CR_RD0
00191 #define RTL_CR_RD_REMOTE_WRITE RTL_CR_RD1
00192 #define RTL_CR_RD_SEND_PACKET 0x18
00193 #define RTL_CR_RD_ABORT_CMPLTE RTL_CR_RD2
00194 #define RTL_CR_SELECT_PAGE0 0x00
00195 #define RTL_CR_SELECT_PAGE1 RTL_CR_PS0
00196 #define RTL_CR_SELECT_PAGE2 RTL_CR_PS1
00197
00198
00199
00200
00201 #define RTL_START() WriteRTL ( RTL_CR , (RTL_CR_START | RTL_CR_RD_ABORT_CMPLTE) )
00202 #define RTL_STOP() WriteRTL ( RTL_CR , (RTL_CR_STOP | RTL_CR_RD_ABORT_CMPLTE) )
00203
00204
00205 typedef enum
00206 {
00207 RTL_RX_IDLE = 0,
00208 RTL_RX_NEW,
00209 RTL_RX_READ_INIT,
00210 RTL_RX_READING
00211 } rtl_rx_stat_t;
00212
00213 typedef enum
00214 {
00215 RTL_TX_IDLE = 0
00216 } rtl_tx_stat_t;
00217
00218 typedef struct
00219 {
00220 nip_net_if_id_t id;
00221 nip_net_if_t *conf;
00222 rtl_rx_stat_t rx_stat;
00223 rtl_tx_stat_t tx_stat;
00224 } rtl_if_stat_t;
00225
00226
00227
00228
00229 extern nip_net_if_id_t rtl_net_if_id;
00230
00231
00232
00233 nip_error_t nip_rtl_send_init ( nip_net_if_id_t net_if_id, void *ll_target_addr, uint16_t type, void *daddr, void *saddr, uint16_t len);
00234 uint16_t nip_rtl_send ( nip_net_if_id_t net_if_id, uint8_t* buffer, uint16_t count);
00235 nip_success_t nip_rtl_read_init ( nip_net_if_id_t net_if_id );
00236 uint16_t nip_rtl_read ( nip_net_if_id_t net_if_id, uint8_t *buffer, uint16_t count);
00237 nip_success_t nip_rtl_open ( nip_net_if_id_t net_if_id );
00238 nip_success_t nip_rtl_close ( nip_net_if_id_t net_if_id );
00239
00240 #endif // _RTL_8019_H
00241
00242